IBIS Macromodel Task Group

Meeting date: 15 March 2016

Members (asterisk for those attending):
ANSYS:                        Dan Dvorscak
                            * Curtis Clark
Broadcom (Avago):             Xingdong Dai
                              Bob Miller
Cadence Design Systems:     * Ambrish Varma
                              Brad Brim
                              Kumar Keshavan
                              Ken Willis
Cisco:                        Seungyong (Brian) Baek
eASIC:                      * David Banas
                              Marc Kowalski
Ericsson:                     Anders Ekholm
GlobalFoundries:              Steve Parker
Intel:                      * Michael Mirmak
Keysight Technologies:      * Fangyi Rao
                            * Radek Biernacki
                            * Ming Yan
Maxim Integrated Products:    Hassan Rafat
Mentor Graphics:            * John Angulo
                            * Arpad Muranyi
Micron Technology:          * Randy Wolff
                              Justin Butterfield
QLogic Corp.:                 James Zhou
                              Andy Joy
SiSoft:                     * Walter Katz
                              Todd Westerhoff
                            * Mike LaBonte
Synopsys:                     Rita Horner
Teraspeed Consulting Group:   Scott McMorrow
Teraspeed Labs:             * Bob Ross
TI:                           Alfred Chong


The meeting was led by Arpad Muranyi.

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Opens:

- None.

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Call for patent disclosure:

- None.

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Review of ARs:

- None

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Review of Meeting Minutes:

- Arpad: Does anyone have any comments or corrections? [none]
- Michael M.: Motion to approve the minutes.
- Arpad: Second.
- Arpad: Anyone opposed? [none]

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New Discussion:

Figure 16 in the IBIS specification:
- Walter: [Sharing his new "Figure 16" presentation]
  - Figure 16 describes a device under test (DUT) and how to connect to the test
    fixture.
  - It describes how the data in the IBIS file are generated.
  - Reasonably good descriptions for this purpose.
  - It does not do a good job of distinguishing between the DUT and the device
    in action (DIA).
    - Rail voltages for DUT vs. rail terminals for DIA?
    - C_comp hookup for DUT vs. C_comp hookup for DIA when rails are not
      constant.
    - What does the ground symbol mean?
      - 20 years ago, at 33MHz, the test fixture ground was "ground," and that
        was good enough because the wavelength was around 20 feet.
    - Now we have [Composite Current], VRM models and other power aware
      features, and much higher frequencies.
  - Focus on the two most common cases, and worry about what the actual DIA
    connections and references look like.
    - "Legacy" case
      - [Pulldown Reference] == [GND Clamp Reference] == 0.0V
      - [Pullup Reference] == [POWER Clamp Reference] == [Voltage Range]
    - ECL case
      - [GND Clamp Reference] == Vee (Data Book)
      - [Pullup Reference] == [POWER Clamp Reference] == [Pulldown Reference]
        ==  Vcc (Data Book)
  - [Slide 4] - Legacy DUT
    - Buffer has pullup_ref and pulldown_ref terminals.
    - pd_ref is hooked up to test fixture ground.
    - No issues with where C_comp and Package Model C are connected.
  - [Slide 5] - Legacy DIA
    - IBIS never tells you how to hook up to a package model or the power
      distribution system.
    - C_comp connected to pulldown_ref node.
    - Simple lumped RLC Package model for signal pin.  C connected to VSS Pin
      somewhere in the package between the die side and board side.
    - Board has power distribution, ground distribution, and the I/O signal
      ultimately goes to the probe/receiver.
    - Logical locations are shown for reference nodes for each section.
      - C_comp -> pulldown ref
      - Package Model -> die side or board side of the package for the Vss Pin.
      - I/O Pin -> its Vss Pin.
      - All these test points have names in the various standards.
    - On the other side of the board, at the probe/receiver, the reference node
      at that point wouldn't really be known to us.
    - No earth ground in this picture.
    - If you use s-parameter models, you need a reference for each of the ports.
      We have to make some assumptions about what the references are if we want
      the current going in and out of the package to go through the correct
      power distribution and account for all the current properly.
    - Becomes challenging to figure out the reference node when doing packaging.
   - [Slide 6] - "Ground Referenced System"
     - Can be mathematically identical to [Slide 5].
     - Effects of the ground distribution end up in the signal or power
       distribution.
     - All of the ground path nodes can be connected to "node 0".
- Discussion: Radek noted that "node 0" need not be the common node.  As long as
  the "output" is the difference between the load pin and the common node,
  that common node could be any floating node.  Radek expressed concern that the
  "output" (load side) of slide five was not fully described/pictured.  He felt
  this could not be ignored.  Walter suggested that we only cared about things
  being specified up to the Pin/board boundary.  Arpad noted, however, that
  implicit in the conversion to the "Ground Referenced System" was that the
  "node 0" approach be adopted throughout the entire circuit.  That is, the
  receiver would have to use the same approach.
- Walter: [Continuing with presentation]
  - [Slide 7] - ECL DUT, Vee and Vcc (example provided by Tom Dagostino)
  - Only real difference is how to hook up the test fixture.
    - Vee = -2.2V relative to test fixture ground.
    - Vcc = +2.2V relative to test fixture ground.
  - [Slide 8] - ECL DIA
    - What does C_comp connect to?  It's logical that it's the same node as the
      gnd_clamp_ref.
    - So the picture is basically identical to the "Legacy" case.
- Discussion: Radek said this C_comp connection was not clearly stated in the
  spec.  Walter agreed, and said "What should it be?" is the question we need to
  try to answer.  Arpad said that C_comp might mean two different things,
  parasitics relative to some substrate, or perhaps output stage drain to source
  capacitance.  If it were the former, C_comp should be connected to that
  substrate's terminal.  If it were the latter, it should be in parallel with
  an I/V curve.  In the ECL case, Arpad suggested the C_comp might be relative
  to some 0V substrate.  Walter agreed we might want to add ways to clarify the
  reference location, but he felt we should come up with some assumptions to use
  if we don't have that info.  He pointed out that most of the split C_comp
  models seem to have simply taken the original C_comp and divided it into two
  halves.  Arpad suggested that we consider forbidding the use of simple C_comp
  altogether with power aware IBIS [Model]s using the [Composite Current] and
  [ISSO_**] keywords.  The reference location for C_comp of any sort is
  irrelevant when the supply rails are ideal, but connecting C_comp to the wrong
  node has serious accuracy consequences when the supply rails are non-ideal.
  Bob noted that several EDA tools document that C_comp goes to absolute ground.
  He said the IBIS spec already has the C_comp_xxx split solution, so we should
  not tinker with changing C_comp usage.  Walter countered that ATM group
  discussions last year had lead to EDA tool manufacturers agreeing that C_comp
  should go to the pulldown_ref of the buffer and not absolute ground, and that
  EDA vendors were waiting on a BIRD to clarify this.

- Arpad: Thank you all for joining.
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Next meeting: 22 March 2016 12:00pm PT
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IBIS Interconnect SPICE Wish List:

1) Simulator directives
